The performance of the parts to be included in computers and other information processing apparatuses, such as SRAMs, DRAMs, processors and switching LSIs, have been improved greatly. However, even with the parts with improved performance, it is difficult to improve the system performance if the signal transmission velocities between the parts are not improved. For example, in recent years, the gap between the working speed of a memory such as an SRAM and a DRAM and the working speed of a processor has been increasing. The gap in speed is hindering the improvement of the performance of computers. The speed of the signal transmission between chips and the speed of the signal transmission between elements and/or circuit blocks within the chips are becoming large factors in limitation of chip performance with the increases in size of the chips. The signal transmission between a peripheral apparatus and a processor or a chip set may be a factor in limitation of the performance of the entire system.
In general, for the signal transmission between circuit blocks, signal transmission between chips or signal transmission within a package, the receiver side recovers clocks from receive data and uses the recovered clocks to perform 0/1 determination on the receive data. At that time, in order to perform proper signal reception, a feedback circuit within the circuit adjusts the phase of the recovered clocks so that the recovered clocks and the receive data may have a certain phase relationship. The method including recovering clocks and determining the receive data by using recovered clocks is called Clock and Data Recovery (CDR). CDR is one of the most important technologies for signal transmission.
CDR employs a circuit that generates an internal clock signal for performing data reception, a comparing circuit that compares the phase of the internal clock signal to the phase of an input data signal, and a feedback circuit that adjusts the phase of the internal clock signal based on the comparison result. More specifically, first of all, in synchronization with the timing of the rising edge of the generated internal clock signal, for example, the data determining circuit performs logical determination (or 0/1 determination) on input data. At this time, data RDT, which is determined in the vicinity of the center of an Eye waveform of the input data, and data BDT, which is determined in the vicinity of the transition point of the input data, are derived. When the RDT changes from 0 to 1 or from 1 to 0, whether the BDT agrees with the RDT data before the transition or the RDT data after the transition may be determined. Thus, whether the phase of the internal clock signal is earlier than the phase of the input data or not is determined. In accordance with the phase relationship between the phase of the internal clock signal and the phase of the input data, the timing of the rising edge of the internal clock signal may be adjusted to control the position of the rising edge of the internal clock signal so that the position may be in the vicinity of the center of the Eye waveform of the input data. Thus, the timings of the internal clock signal may be adjusted in accordance with the jitter of input data, whereby the data determination may be performed accurately.
In the configuration of CDR in the past, the ability for detecting the amount of jitter of the input data depends on the phase shift precision of an internal clock signal. For example, if the phase resolution of the internal clock signal is 6 bits, the phase of the internal clock signal may be changed in steps of 0.015625 Unit Intervals (UI). In other words, the jitter may be detected with 0.015625 UI precision. A CDR circuit having a feedback configuration that dynamically changes the sampling timing of input data may require the high detection sensitivity as in this example.
In the CDR circuit in the configuration in the past, in order to change the phase of a clock signal, an analog component circuit such as a Phase Interpolator (PI) has been used. However, because the operations by the PI are susceptible to the variations among processes or changes in power supply voltage, the characteristics based on the phase of the CDR circuit also changes. The technology relating to the clock reproduction has been disclosed in Hideki Takauchi, “A CMOS Multi-Channel 10 Gb/s Transceiver,” 2003 IEEE International Solid-State Circuits Conference, 2003.